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What advantages do you get from our Achiever Papers’ services? The MII naming convention may be thought of as a generic brand name that is also used for products i. Each of these will be detailed further in the next section. Similarly, the system-level requirement of the transmission medium, such as copper cable and fiber-optics, needs to be considered.
To demonstrate this point, you should check the product page of the selected PHY in the design example, which is the KSZ There is no need to mention the MDI side as this is relatively clearer when it comes to selecting the correct PHY, with the choice between fiber and copper cable interfaces. Reading and understanding any gigabit PHY datasheet may not appear that easy at first glance since there will be a lot of standard-defined properties listed in the features section.
We will try to describe some of these briefly and if you feel some extra information is needed for your specific application, just google the appropriate keyword:. Gigabit Ethernet uses PAM-5 modulation that uses five voltage levels and encodes two bits per clock cycle using four different voltage levels in each pair; the fifth voltage level is used for error-correction.
So, using the same Baud rate and clock frequency as the Fast Ethernet, the Gigabit Ethernet uses all available resources more efficiently and increases the link speed, all the while keeping within the certified limits of the relatively cheap Cat5 cable rather than needing to use more expensive higher category cables.
Also, additional clock references such as 2. It is always a good idea to double-check the datasheet to see if it has a built-in crystal driver that makes it able to use crystal. Generally, the accuracy requirements are advised to be better than 50 ppm, and utilizing an oscillator may make the layout easier. Again, it is a trade-off for designers in terms of price, stability, and layout effort.
You have to be careful to check the crystal load capacitance if you select this option. It is strongly recommended to check the datasheet carefully for the strap options since these are vendor-dependent and may be subject to change between each device.
The crucial point here is to adjust the required reset time for the strap pins to settle at the desired voltage level, which is easily adjusted using an RC delay circuitry. Another point related to PHY selection is to check whether it has internal termination resistors or not.
The MDI uses balanced differential pairs, and so if the PHY does not have on-chip termination resistors, parallel split termination preferred to filter common-mode noise must be added to the board. Similarly, the xMII interface should have series termination resistors, either on-chip or on-board. As briefly mentioned, while describing the use of the magnetics center-tap, there are two types of line-driver available for gigabit Ethernet: Current Mode and Voltage Mode.
The designer should check the PHY line driver for a magnetics center-tap and split termination center-tap connection. Since voltage-mode drivers have various advantages over current-mode, nowadays, this type of line driver is more prevalent among devices.
However, the designer should still be aware of the current-mode line driver requirements for different design aspects. Other analog, digital, and IO supplies are usually selectable from 3.
To allow single-supply operation, the device may have an integrated LDO controller e. If the board already has a separate 1.
As FET selection is strictly related to the controller, designers should follow the recommendations within the datasheet for FET specifications. After selecting the correct PHY to fulfill the requirements and following the above recommendations, the schematic design is fairly standard regardless of the chosen device and follows these steps:.
Some explanatory notes and device-specific pin connections are given inside the schematic. Transmitted and received signals must be synchronized using clock signals. It is vital to bear in mind that evolving technology not only increases bandwidth requirements but can also result in a lot of interfaces in use at the same time.
This is why having at least one GPIO pin may be valuable to future-proof the overall design. Signal descriptions are given in Table 2 below. For gigabit communications, data is clocked on both the falling and rising edges of the MHz clock, which results in a halving of the data signal count.
Both of these are source-synchronized clock signals, and they use both the falling and rising edges of the clock, which makes timing more critical. If it is not supported by one or both devices, then the delay must be applied as part of the PCB layout by using correctly designed serpentines, as shown in Figure 15 below.
Always double-check the naming conventions before designing the layout. Single-ended parallel bus topologies need series termination on the driver side to match both the output driver impedance and the line characteristic impedance, to prevent reflections and EMI problems. Designers should check the PHY and MAC datasheet for the presence of internal termination resistors, and if they do not exist, they must be placed on-board. Generally, values between 20 ohms and 40 ohms will work, but some trial and error may be needed to get the best performance.
SGMII reduces the pin count and increases the speed, but the downside is that the layout is more complicated than for the xMII methods. Most SerDes high-speed interfaces require capacitive coupling to prevent receiver-transmitter common-mode voltage mismatches. It is recommended to have at least place holders for nF series capacitors close to the TX side of the SGMII pairs, along with parallel termination resistors according to the differential pair impedance usually ohms or ohms..
This interface is similar to the I2C bus and is used by upper-level devices such as the MAC to acquire the PHY status and to program the PHY registers to tune changeable run-time parameters like clock settings and fix-up routines. It is worth mentioning that you may not need to add multiple Ethernet PHY and MAC devices on your circuit board unless there are strict requirements for the physical separation of the interfaces.
The best practice is to use isolation transformers for all the PHY interfaces located on the board, similar to the RJ connector operation. However, this method is expensive and uses up a lot of board space. Instead, all the pairs are capacitively coupled using series nF capacitors. Although it is not guaranteed to work over long distances, in theory, it works very well over relatively short distances. After reading hundreds of datasheet pages, you have a perfectly designed schematic that meets all the requirements and suggestions the manufacturers have suggested – however, all that effort can easily be ruined or have degraded performance due to fundamental layout failures.
For the design of a Gigabit Ethernet interface, there are impedance controlled differential and single-ended signals to be considered, as well as some length matching and maximum length limitations. Most of the time, these requirements are automatically fulfilled by the sensible placement of the components unless the designer tries to override this approach. The problem is that if general layout rules are not obeyed such as not using solid reference planes for Ethernet impedance controlled traces , it is a waste of effort to strictly match trace lengths or keep them below the maximum length limits.
Therefore, we will briefly describe the generic high-speed layout rules before specific gigabit Ethernet layout requirements are discussed to provide a foundation for the more specific requirements. High-speed switching digital ICs demand transient currents. The main rule is to place bypass capacitors as close as possible to all the supply pins, with at least one 10 nF and nF capacitor for each pin.
For multi-layer boards , there are separate power and ground planes, and so vias will inevitably be used in the path used to supply power. Since vias also have an inductive component, no via should be used between a bypass capacitor and its associated supply pin. This rule is illustrated in Figure 20 below.
The basic rule for all electronics is that the current flowing in the circuit always returns to its source. So, there should always be a return path for the signals, and this return path will form a loop antenna with the outbound signal path. Based on both the theory and experimental evidence for high-speed signals, the current return path will follow the trace on the layer that is beneath it.
In other words, its reference plane. Keeping a solid reference plane below any high-speed signal routing will minimize the loop area and prevent any impedance discontinuity. If for any reason, plane voids are created beneath a high-speed trace, stitching capacitors should be used to create a return path. The use of stitching capacitors is also recommended if the power plane is also the reference plane for a high-speed signal that creates a return path to the current source.
These rules are illustrated in Figure 21 below, showing bad practices on the left and good practices on the right. This does not mean that it is impossible to use a two-layer PCB for a gigabit Ethernet interface. Each trace on the PCB will have a characteristic impedance, calculated with respect to its reference plane. Altium Designer has impedance calculation tools built-in; however, for high speed signals, there are many other tools to assist with simulating performance and verifying calculations.
The required trace width and dielectric spacing may be easily calculated for required impedance according to the PCB stack-up. At the same time, traces, serpentines, and pairs are better if they are separated as much as possible to prevent any crosstalk and to increase their glitch immunity.
Also, the use of stubs should be avoided. Finally, to prevent crosstalk between adjacent layers, any parallel signal routing along layers should be avoided unless there is a solid plane between them.
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